A voltage controlled oscillator (VCO) is an electrical oscillator that generates an oscillatory signal having a frequency which is dependent on a control voltage. VCOs provide important functions in communication systems and other electronic systems. They are used in both analog and digital systems, and are essential components in virtually every radio frequency (RF) communication system.
FIG. 1 is a schematic drawing of a commonly used VCO 100, as is known in the art. The VCO 100 comprises an inductive-capacitive (L-C) tank circuit 102, first and second cross-coupled transistors 112 and 114, and a current source 116. The tank circuit 102 includes first and second inductors 104 and 106 and first and second varactor diodes 108 and 110. As will be explained in more detail below, the varactor diodes are special types of diodes configured to provide a variable capacitance depending on the voltage applied across their terminals.
The frequency of oscillation of the VCO 100 is determined by the resonant frequency of the tank circuit 102. More specifically, the frequency of oscillation of the VCO 100 is generally determined by the equation: ω=1/√{square root over (LC)}, where L represents the sum of the inductances of the first and second inductors 104, 106, and C represents the capacitance contributed by the first and second varactor diodes 108, 110.
Ideally the tank circuit 102 has zero resistance, and the oscillator 100 oscillates in perpetuity once it is set into oscillation. However, because the capacitors and inductors of the tank circuit 102 are not ideal (they each include some finite amount of resistance), the oscillator 100 cannot continue to oscillate unabated absent some mechanism to counteract the non-idealities. This is the purpose of the first and second cross-coupled transistors 112, 114, which together provide a negative resistance that effectively cancels out loss resistances contributed by the tank circuit components.
VCOs are typically configured within phase-locked loop (PLLs), to counteract a tendency of the output frequency of the VCO to drift. The PLL prevents frequency drift by forcing the VCO to lock to a highly stable reference frequency, e.g., derived from the resonant frequency of mechanical vibration of a crystal, such as quartz. Multiples of the reference frequency can also be generated, by including a frequency divider in the feedback loop of the PLL.
FIG. 2 is a block diagram illustrating the principal elements of a PLL 200. The PLL 200 comprises a phase detector 202, a loop filter 204, a VCO 206, and a frequency divider 208. A first input of the phase detector 202 is configured to receive a reference frequency signal having a precise and stable frequency, fref. A second input of the phase detector 202 is configured to receive a feedback signal having a frequency f/N, where f represents the frequency of the VCO output signal and N is a divisor provided by the frequency divider 208. The frequency divider 208 is controlled by a tuning control signal (labeled “TUNING” in the drawing), which allows the VCO 206 to be tuned to different frequencies, f.
During operation the VCO 206 tunes to frequencies corresponding to voltages of a control signal, Vtune, applied to the VCO's voltage control input. The frequency of the VCO output is divided by the frequency divider circuit 208 to provide a signal having a divided frequency, f/N. This divided frequency signal is applied to the second input of the phase detector 202, while the reference frequency signal is applied to the first input of the phase detector 202. In response to the applied signals, the phase detector 202 generates a semi-periodic phase difference signal (or ‘error’ signal) if the divided frequency, f/N, deviates from the reference signal frequency, fref. The error signal includes a measure of the degree to which the two frequencies are misaligned. The loop filter 204 filters the error signal, and provides an adjusted control signal, Vtune, having a voltage level that causes the VCO 206 to correct its output frequency in a direction that reduces the frequency misalignment. The corrected VCO output signal is fed back to the frequency divider circuit 208, and the phase detection and error reduction processes described above are repeated until f/N is forced to equal the reference signal frequency fref. When this condition occurs the VCO output frequency, f, is equal to N×fref and the PLL 200 is said to be “locked.”
PLLs are used in a variety of applications, including frequency synthesis, pulse synchronization of signals from mass storage devices, and regeneration of signals. They are also critical components of RF transmitters and receivers. FIG. 3 illustrates, for example, how a PLL 312 is configured as a phase modulator within a phase path of a polar transmitter 300. The polar transmitter 300 comprises a baseband processor 302; a rectangular-to-polar converter 304; an amplitude path (or ‘envelope path’) including an envelope path digital-to-analog converter (DAC) 306 and an envelope modulator 308; a phase path including a phase path DAC 310 and the PLL 312; an RF power amplifier (RF PA) 314; and an antenna 316. An output of the envelope modulator 308 in the amplitude path of the transmitter 300 is coupled to a power control input of the RF PA 314, and the output of the PLL 312 is coupled to an RF input of the RF PA 314.
The polar transmitter 300 operates as follows. First, the baseband processor 302 receives a digital message from a digital message source and generates a sequence of in-phase (I-phase) and quadrature-phase (Q-phase) symbols from the digital message according to a predetermined baseband modulation scheme. The rectangular-to-polar converter 304, which typically comprises a Coordinate Rotation Digital Computer (CORDIC) conversion process, converts the rectangular baseband modulated signals, (x, y)=(I, Q), to polar form: (ρ, θ)=
      (                                                      I              2                        +                          Q              2                                ,                    ⁢                        tan                      -            1                          ⁡                  (                      Q            I                    )                      )    .The resulting envelope and phase component signals are then separately processed in the amplitude and phase paths of the transmitter 300.
In the amplitude path, the envelope path DAC 306 converts the digital envelope component signal into an analog envelope component signal. The analog envelope component signal is used by the envelope modulator 308 to modulate a power supply voltage, Vsupply, according to the shape (i.e., amplitude variations) of the envelope component signal. The modulated power supply voltage signal is applied to the power control input of the RF PA 314. Meanwhile, in the phase path, the phase path DAC 310 operates to convert the phase component signal into an analog phase component signal. The analog phase component signal is applied to the PLL 312, specifically to the phase detector 316 of the PLL 312, to generate a control voltage signal proportional to the phase error between the phase modulation signal and the divided frequency signal from the output of the frequency divider 322. Similar to the description of the PLL 200 in FIG. 2 above, the VCO 320 in the polar transmitter 300 in FIG. 3 responds to the control voltage signal by adjusting its output frequency according to the magnitude of the control signal. When the PLL 312 is locked, the VCO 314 provides a phase modulated output signal, cos(ωct+θ(t)), where ωc represents the carrier frequency (in radians/sec) of the RF carrier signal specified by the tuning command at the tuning input of the frequency divider 322, and θ(t) represents the phase modulation applied to the carrier signal.
The RF phase modulated signal, cos(ωct+θ(t)), from the phase path of the polar transmitter 300 is recombined with the envelope information from the amplitude path at the RF PA 314, to provide the desired angle modulated output signal, A(t)cos(ωct+θ(t)), where A(t) represents the time varying envelope variation imposed on the phase modulated signal, cos(ωct+θ(t)). The RF PA 314 is usually configured to operate as a switch-mode amplifier. Therefore, the power of the angle modulated RF output signal of the polar modulator 300 is directly controlled by the modulated power supply voltage applied to the power control input of the RF PA 314.
Application of phase modulation to the RF carrier in the manner described above proves to be satisfactory for narrowband applications. However, in wideband applications the effective tuning capability of the VCO is limited by the capacitance versus voltage (CV) characteristics of its varactor diodes. Wideband applications require the varactor diodes to be operated over a wider voltage range than in narrowband applications. However, the varactor diode capacitances relate linearly to the voltage applied across them, Vtune, only over a narrow voltage range (see FIG. 4). This linear tuning range is only on the order of about a diode drop (i.e., 0.7 V).
The nonlinear CV relationship of the VCO varactor diodes outside the linear range results in a tuning sensitivity, Kv, which varies depending on what the value of the control signal, Vtune, is. This variation in Kv leads to nonlinear operation of the VCO, which is a highly undesirable condition since the nonlinearities cause PM-PM distortion (i.e., phase modulation errors caused by an output relating nonlinearly to its input) in the desired final phase modulated output signal. There are prior art techniques that can be used to limit the effects of variations in tuning sensitivity, Kv. However, those techniques result in a wide variation in loop settling times, which effectively limits the tuning bandwidth capability of the VCO and PLL.
Wide bandwidth and fast, well-controlled settling time capabilities are needed to generate and process the types of waveforms used in current and next generation wireless communications standards. The waveform types used in third generation (3G) cellular systems (e.g., signals used in Wideband Code Division Multiple Access (W-CDMA) systems and according to the High-Speed Downlink Packet Access (HSDPA) protocol), and other high data rate and next-generation cellular systems communication systems can exhibit considerable signal activity in the vicinity of the origin of the signal plane. The time rate of change of the phase of these signals can also be quite high. In extreme circumstances in which the signal passes through the origin, an instantaneous phase reversal corresponding to an essentially infinite time rate of change of the signal phase can occur. Unfortunately, accurately and precisely producing waveforms having these characteristics using the prior art tunable VCO/PLL apparatus described above is difficult or even impossible to achieve due to the limited linear tuning range capability of the VCO and PLL.
Considering the foregoing limitations and problems of the prior art, therefore, it would be desirable to have wideband phase modulation methods and apparatus which avoid signal distortions caused by nonlinear VCO operation.